Programmable FIFO buffer
US4750149A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1986 |
| Grant date | Jun 7, 1988 |
| Priority date | — |
| Expiry date | Jul 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable FIFO buffer is disclosed which including a (serial) input register, a control register, a (parallel-input parallel-output-type) FIFO buffer, a (serial) output register, and another control register. The input register is for receiving signals representing in serial format a word of data and for developing signals representing the data word converted to parallel format. The former control register is for controlling the serial-to-parallel conversion process. The (parallel-input parallel-output-type) FIFO buffer is for storing the data word. The output register is for receiving from the buffer, signals representing in parallel format a word of data stored in the buffer and for developing signals representing the stored data word converted to serial format. And, the latter control register is for controlling the parallel-to-serial conversion process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.