Display device comprising a delaying circuit to retard signal voltage application to part of signal electrodes
US4750813A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1987 |
| Grant date | Jun 14, 1988 |
| Priority date | — |
| Expiry date | Feb 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device consisting of a plurality of scanning electrodes, a plurality of signal electrodes, a driving circuit feeding these electrodes with a scanning voltage and a signal voltage applied thereto, display elements having a pair of electrodes opposite to each other, which are disposed on the intersecting portion of the signal electrodes with the scanning electrodes, and switching elements controlling the feeding of one of the electrodes with the signal voltage, depending on the scanning voltage, comprises further a delaying circuit, which retards the timing of applying the signal voltage applied to a part of the signal electrodes, which are distant from the input terminal of the scanning voltage, with respect to the timing of applying the scanning voltage applied to the scanning electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.