Process of forming a compliant lead frame for array-type semiconductor packages
US4751199A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1987 |
| Grant date | Jun 14, 1988 |
| Priority date | — |
| Expiry date | Jan 21, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53174
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A lead frame that is suited for use on array types of integrated circuit packages to provide a high degree of compliance for absorbing mechanical stress induced by thermal changes includes a series of individual terminal elements that are connected in a strip form by means of break tabs disposed between adjacent elements. Each terminal element provides two spaced, generally parallel mounting surfaces that are resiliently connected to one another by means of an integral intermediate section. While the terminal elements are interconnected in strip form, one of the mounting surfaces of each element can be bonded to an associated attachment region on the semiconductor substrate. After all of the terminals of the strip have been so bonded, the break tabs between adjacent terminals can be removed to thereby separate the terminals from one another. The package which then results contains discrete compliant terminals which are suitable for subsequent surface attachment to the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.