Self-timing circuit
US4751407A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1986 |
| Grant date | Jun 14, 1988 |
| Priority date | — |
| Expiry date | Dec 19, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing circuit is disclosed for use with an external circuit that provides a precharge/evaluation complete signal indicative of precharge completion and evaluation completion. The timing circuit is responsive to a clock signal and the precharge/evaluation complete signal provided by the external circuit, and includes a clock enabling circuit responsive to the clock signal and the precharge/evaluation complete signal for providing a clock enable signal having first and second states respectively indicative of (a) a predetermined condition wherein evaluation has been completed and the clock signal is at a predetermined level, and (b) precharge completion. A level shifting circuit is responsive to the clock signal and the clock enable signal and provides a phase control signal to the pseudo CMOS circuit, where such phase control signal defines (a) a precharge phase in response to said clock enable signal indicating the predetermined condition and the clock signal providing a predetermined transition, and (b) an evaluation phase in response to the precharge/evaluation complete signal indicating completion of precharging. A latching circuit is responsive to the clock enable signal and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.