Intelligent phase-locked loop
US4752748A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1987 |
| Grant date | Jun 21, 1988 |
| Priority date | — |
| Expiry date | Apr 16, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An intelligent phase-locked loop performs adaptive transfer function parameter selection and fault tolerant self-monitoring within the phase error filtering algorithm. The algorithm includes a capture mode, at least one align mode and an operate mode. The capture mode shifts to the align mode if the phase error limit is not exceeded at the end of a first period of time. The align mode switches back to the capture mode if a reverse phase error relation is met during the mode. At the end of the align mode, the algorithm switches to the operate mode if a forward phase error relation is met. The operate mode continues indefinitely. However, a switchback to the align mode is made if an out of lock phase error limit is exceeded for the operate mode. The bandwidths of the transfer function of the loop are adapted for each of the modes so that the capture mode is the broadest bandwidth, the align mode is an intermediate bandwidth and the operate mode is a narrow bandwidth. Further, according to the invention, the algorithm performs hardware fault monitoring based on statistical processing carried out during the phase error filtering cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.