Semiconductor integrated circuit device having a carrier trapping trench arrangement
US4752819A · kind A · utility
13Cited by
11References
24Claims
0Family size
Assignees
Inventor
Key dates
| Filing date | Feb 19, 1987 |
| Grant date | Jun 21, 1988 |
| Priority date | — |
| Expiry date | Feb 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
Herein disclosed is a DRAM which has such a carrier trapping region around a memory cell array as can trap minority carriers deep in a semiconductor substrate so that the minority carriers to be generated in the semiconductor substrate by alpha rays may be sufficiently trapped. The memory cell of the DRAM has a capacitor which is partially formed of the semiconductor substrate. The carrier trapping region is formed by making use of trenches or a well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.