Four-quadrant multiplier using a CMOS D/A converter
US4752900A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1986 |
| Grant date | Jun 21, 1988 |
| Priority date | — |
| Expiry date | May 19, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four-quadrant multiplier uses a CMOS digital-to-analog converter (DAC) and just one operational amplifier. The back gates of the CMOS switches in the DAC are biased in the "off" condition during a substantial voltage swing at the output of the DAC. In one embodiment, the back gates of the CMOS switches are held at about -5 V with respect to the output lines, and the logic low level to the off switch also is set at -5 V relative to the output lines. The DAC connections are "reversed" so as to receive the analog input across the terminals intended as the DAC's output, with the inputs of the operational amplifier being connected across the reference voltage terminal and a feedback or output terminal of the DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.