High-speed multiplier having carry-save adder circuit
US4752905A · kind A · utility
32Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1985 |
| Grant date | Jun 21, 1988 |
| Priority date | — |
| Expiry date | Nov 6, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.