Frame buffer memory
US4755810A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1985 |
| Grant date | Jul 5, 1988 |
| Priority date | — |
| Expiry date | Apr 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer memory has a random access memory (RAM) for storing pixel data words, each word containing pixel data corresponding to a separate set of a plurality pixels along a horizontal raster line of a screen display. Each word is separately addressed.The RAM is organized into tiles, with each tile comprising an array of pixel data word rows and columns corresponding to a separate rectangular subset of horizontally and vertically contiguous display pixels. The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel word row within each tile is addressed, while and a second subset of the column address determines which pixel word column within each tile is addressed. All other bits of the row and column addresses determine which tile is addressed. Means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that words within a selected tile row or column may be successively addressed allowing rapid reading and writing of sequences of pixel data corresponding to contiguous rows or columns of display pixels. A first-i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.