Hierarchical cache memory system and method
US4755930A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1985 |
| Grant date | Jul 5, 1988 |
| Priority date | — |
| Expiry date | Jun 27, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.