Asynchronous/synchronous data receiver circuit
US4756010A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1985 |
| Grant date | Jul 5, 1988 |
| Priority date | — |
| Expiry date | Nov 7, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a communications system wherein a transmitted message is preceeded only by an address, an asynchronous circuit detects the address and provides an initializing signal to a synchronous clock recovery circuit so that the first bit of the recovered clock signal is synchronized to the first bit of the message. During the transmission of the message the synchronous clock recovery circuit makes minor adjustments to the phase of the recovered clock to maintain synchronization between the recovered clock and the message. At the termination of the message, the synchronous clock recovery circuit is inhibited until the asynchronous circuit detects another address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.