Amorphous thin film transistor device
US4757361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1986 |
| Grant date | Jul 12, 1988 |
| Priority date | — |
| Expiry date | Jul 23, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor technology where a gate member on a substrate surface is in electric field influenceable proximity to active semiconductor devices in the direction normal to the substrate surface and the ohmic electrodes of the active device are parallel with the substrate surface. The gate is formed on the substrate and conformal coatings of insulator and semiconductor are provided over it. A metal is deposited from the direction normal to the surface that is thicker in the horizontal dimension than the vertical so as to be susceptible to an erosion operation such as a dip etch which separates the metal into self-aligned contact areas on each side of a semiconductor device channel without additional masking. Self-alignment of the source, drain and gate can be achieved by insulator additions above and under the gate fabricated without additional masking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.