Logical arrangement for controlling use of different system displays by main proessor and coprocessor
US4757441A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1987 |
| Grant date | Jul 12, 1988 |
| Priority date | — |
| Expiry date | Jun 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that hav…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.