Apparatus for estimating the square root of digital samples
US4757467A · kind A · utility
15Cited by
4References
11Claims
0Family size
Assignee
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Key dates
| Filing date | May 15, 1986 |
| Grant date | Jul 12, 1988 |
| Priority date | — |
| Expiry date | May 15, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K).sup.2) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K).sup.2 is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.