Polyphase parity generator circuit
US4757504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1986 |
| Grant date | Jul 12, 1988 |
| Priority date | — |
| Expiry date | Apr 21, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.