Programmable logic array with added array of gates and added output routing flexibility
US4758746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1985 |
| Grant date | Jul 19, 1988 |
| Priority date | — |
| Expiry date | Aug 12, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.sub.1 through O.sub.10) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.