Page mapping system
US4758946A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1986 |
| Grant date | Jul 19, 1988 |
| Priority date | — |
| Expiry date | Sep 26, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page mapping system for virtual memory that requires only one address to be continually resident in memory per user subspace and permits the size of a process subspace to be varied dynamically. The system provides a tree of page map pages ("PM pages") with only the very root of the tree (a base address entry) being required to be in physical memory. Depending on the size of the space, the page map includes, as well as the base address entry, a number of paged levels with one PM page at the highest level (to which PM page the base address entry points). The page map entries (PMEs) of the first level PM pages point directly to the physical pages. Each PME in a higher level of the page map points to a PM page at a lower level in the page map, whereupon the page map may grow geometrically from the highest level to the first level. The PMEs for pages or PM pages that are not allocated are so marked. The number of levels of the page map is dynamic, and may be increased should the subspace need to be increased to a size that exceeds the maximum size that can be mapped by the page map of a present number of levels. The page map includes within it a representation of the number of levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.