Asynchronous-to-synchronous digital data multiplexer/demultiplexer with asynchronous clock regeneration
US4759014A · kind A · utility
34Cited by
10References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1987 |
| Grant date | Jul 19, 1988 |
| Priority date | — |
| Expiry date | May 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/24
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Digital data is received on a plurality of input channels at unrelated, asynchronous input clock rates. The data is multiplexed and transmitted via one or more synchronous parallel channels, together with encoded information related to the original asynchronous input clock rate on each channel. The data received from the synchronous channels is demultiplexed and redistributed to proper output channels and clocked out therefrom at rates derived from the encoded and reconstituted asynchronous clock rate information from each channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.