Method of forming edge-sealed multi-layer structure while protecting adjacent region by screen oxide layer
US4760034A · kind A · utility
16Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1987 |
| Grant date | Jul 26, 1988 |
| Priority date | — |
| Expiry date | Jun 15, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
Abstract
A process for forming a DRAM cell having a capacitor adjacent a field effect transistor (FET), wherein the FET fabrication area is protected from adverse effects of the capacitor formation. The process is misalignment tolerant and provides FETs with appreciably lower defects in the substrate beneath the FET. Additionally, the process eliminates the need to stop an etching operation on a thin capacitor dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.