Multiplex interface for a communication controller
US4760573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1986 |
| Grant date | Jul 26, 1988 |
| Priority date | — |
| Expiry date | Nov 13, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slots are assigned to each user line, the structure of the two slots is identical for all types of user lines and includes an n-bit data slot having a variable number x of valid bits depending upon the line speed of the user line assigned to the data slot and indicated by a variable delimiter pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n-x-1) bits set at the second binary value (0) adjacent to said first delimiting bit, and an n-bit control slot having a first bit used as a global validation bit in case the data slot comprises n valid bits (x=n), this bit being set at the first binary value (1) when the data slot comprises n valid bits and at the second binary value (0) if it comprises less than n valid bits, and the n-1 following bits are used for exchanging control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.