Memory circuit enchancement to stablize the signal lines with additional capacitance
US4761571A · kind A · utility
6Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1985 |
| Grant date | Aug 2, 1988 |
| Priority date | — |
| Expiry date | Dec 19, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having voltage level circuit switching portions operated between signal lines stabilized by additional capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.