Method of obtaining surface mount component planarity
US4761880A · kind A · utility
3Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1986 |
| Grant date | Aug 9, 1988 |
| Priority date | — |
| Expiry date | Dec 8, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A packaging technique for finely leaded electronic devices for attachment by surface methods to printed circuit boards is disclosed wherein the leads are imbedded in solder foil prior to the completion of lead forming operations so as to maintain planarity of the leads and to prevent damage thereto during handling, placement and attachment processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.