Bus device for use in a computer system having a synchronous bus
US4763249A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1986 |
| Grant date | Aug 9, 1988 |
| Priority date | — |
| Expiry date | Oct 29, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.