Patent · US Expired

Integrated dynamic semiconductor memory with complementary circuitry and word line voltage control

US4763301A · kind A · utility

1Cited by

5References

5Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Alfred Schuetz · Fulda, DE
Wolfgang Mueller · Garden City, US
Ewald Soutschek · Haar, DE

Key dates

Filing date	Jul 1, 1985
Grant date	Aug 9, 1988
Priority date	—
Expiry date	Jul 1, 2005

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4085
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit for a dynamic semiconductor random access memory, constructed of complementary transistors, has memory cells connected to bit lines by way of individual selection transistors of a first channel type, the operation of which is controlled by word lines. The voltage on the word lines is controlled by a first switching transistor of a second channel type, controlled by the output of a decoder. The first switching transistor is connected between the word line and a selection voltage which alternates between two voltage values of different operational signs, and the gate of the first switching transistor is connected through a capacitor to the selection voltage and through a second switching transistor having its gate at reference potential, to the output of the decoder.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.