Method for fabricating self-aligned, conformal metallization of semiconductor wafer
US4764484A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 8, 1987 |
| Grant date | Aug 16, 1988 |
| Priority date | — |
| Expiry date | Oct 8, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer (10), a thin silicon layer (16), and then a second dielectric layer (18) are deposited on the upper surface of a substrate. A trench (20) is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole (26) is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion (24a) of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal (28) such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.