Heterojunction field effect transistor with two-dimensional electron layer
US4764796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1986 |
| Grant date | Aug 16, 1988 |
| Priority date | — |
| Expiry date | Dec 9, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/4732
Abstract
A field effect transistor utilizing semiconductor hetero junction having a high mutual conductance, low noise, and a reduced source resistance, has a gallium indium arsenide mixed crystal semiconductor layer (23) providing a current path, low resistance indium phosphide layers formed on or under the gallium indium arsenide mixed crystal semiconductor layer (23) by ion-implantation for achieving the reduced source resistance, a source electrode (6), a gate electrode (5) and a drain electrode (7) which are formed on the surface of an uppermost aluminum indium arsenide mixed crystal semiconductor layer (24), an ion-implanted layer located at least in a region to form the reduced source resistance between the source electrode (6) and a two-dimensional electron layer (8) within the gallium indium arsenide mixed crystal semiconductor layer (23).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.