Test interface for an MOS technology integrated circuit
US4764924A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 1986 |
| Grant date | Aug 16, 1988 |
| Priority date | — |
| Expiry date | Oct 10, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This interface enables the integrated circuit with which it is associated to be placed in a test configuration by applying to its test input terminal (2) a voltage higher than the power supply voltage (V.sub.cc) of the circuitry. In the rest state, the interface then supplies a low logic level to its output terminal (5). If the test command voltage is applied, this level changes state. The interface comprises, in particular, two transistors (M.sub.1, M.sub.2) of opposite types of conductivity which are fed by a constant current source (10, M.sub.5, M.sub.6). The interface switches over when the input transistor (M.sub.1) is put into the conducting state by the test command voltage so as to divert a fraction of the current flowing in the second transistor (M.sub.2). The input terminal (2) can at the same time be a functional input terminal of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.