Method and apparatus for testing integrated circuits

US4764925A · kind A · utility

Assignee

• Fairchild Camera & Instrument Corp. · US

Inventors

• Scott Grimes · Richmond, US
• Lary J. Beaulieu · Cocoa, US
• Douglas Reed · New York, US

Key dates

• Filing date: Jun 14, 1984
• Grant date: Aug 16, 1988
• Expiry date: Jun 14, 2004

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R35/00
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head. If the device passes the orientation test or is determined by the orientation test to be simply misoriented (inserted upside-down), it is then subjected to a prescribed functionality check (with the direction of orientation taken into account). The processor architecture of the test apparatus is configured to maximize the systems's ability to rapidly sequence through the test vectors for the…