Microprocessor having variable data width
US4766538A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1985 |
| Grant date | Aug 23, 1988 |
| Priority date | — |
| Expiry date | Dec 10, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data width instruction from the command execution unit and modifies timings of them according to an externally supplied data width selection signal and transmits modified address, data, memory access instruction and data width instruction signals to the address output logic, the data input/output logic and the bus controller. The bus cycle changeover circuit comprises a cycle control circuit which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit which selects upper/lower parts of the data bus according to an output signal of the cycle control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.