Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer
US4769337A · kind A · utility
10Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 8, 1987 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | May 8, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, comprises the process of forming first and second well regions, which are of N-type and P-type, respectively, in a silicon body, forming a base layer of P-type in the first well region, forming an emitter layer of N-type in the base layer, forming source and drain layers of N-type in the second well region, forming a polysilicon emitter electrode on the emitter layer, and ion-implanting impurities of N-type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.