Integrated circuit clock bus layout delay system
US4769558A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1986 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | Jul 9, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock bus system fabricated on an integrated circuit for distributing a train of clock pulses to circuit elements on the integrated circuit. An input terminal is connected to receive a train of clock pulses. All of the circuit elements are circumscribed by a clock bus which is also coupled to each of the circuit elements. A plurality of distribution legs which include clock bus drivers are coupled to the input terminal by conductors and provide the train of clock pulses to the clock bus at spaced-apart locations. The distribution legs coupled to the input terminal by shorter conductors include delay elements for delaying the clock pulse train by time periods corresponding to the delay inherent in longer conductors. The clock pulse trains provided to the clock bus by the distribution legs are thereby synchronized with respect to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.