Video display control circuit arrangement
US4769637A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1985 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | Nov 26, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/346
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. At the same time those signals are used to refresh the memory. During the alternate cycles (between refresh cycles) there may be a burst of signals from the signal path circuitry chip to write information into the bit map memory at some new address to effect scrolling. Instead of performing scrolling in the alternate cycles, information may be erased from a region. In the alternative there may be a burst of signals from …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.