Address conversion for a multiprocessor system having scalar and vector processors
US4769770A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1985 |
| Grant date | Sep 6, 1988 |
| Priority date | — |
| Expiry date | Dec 11, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.