Digital signal processor with parallel multipliers
US4771379A · kind A · utility
159Cited by
1References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 21, 1986 |
| Grant date | Sep 13, 1988 |
| Priority date | — |
| Expiry date | Oct 21, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.