Method of simulating additional processors in a SIMD parallel processor array
US4773038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1986 |
| Grant date | Sep 20, 1988 |
| Priority date | — |
| Expiry date | Feb 24, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described for simulating additional processors in a SIMD computer by dividing the memory associated with each processor into a plurality of sub-memories and then operating on each sub-memory in succession as if it were associated with a separate processor. Thus, a first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at a first location or locations in the first sub-memory. Thereafter, the same first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at the same first location in a second sub-memory. And so forth for each of the sub-memories. By operating a SIMD computer in this fashion, it is possible in effect to vary the number of processors in the array so as to provide the number of processors required for a problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.