Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
US4774653A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 1985 |
| Grant date | Sep 27, 1988 |
| Priority date | — |
| Expiry date | Aug 7, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid hardware/software implementation of a translation look-aside buffer (TLB) is provided which improves the efficiency of address translation in a computing system utilizing a virtually addressed memory. To access a physical memory location a processor first attempts to fetch a virtual-to-physical address translation from a primary TLB. If the address translation is not in the primary TLB, the processor attempts to fetch the address translation from a secondary TLB. If the address translation is not in the secondary TLB, a trap is generated, after which the processor searches a virtual address translation table for the address translation. Through the use of the present invention, complex hashing routines can be used to address entries in a virtual address translation table (VATT) within the system's physical memory, without increasing the complexity or significantly reducing the performance of the TLB fetch hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.