Surface planarization method for VLSI technology

US4775550A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• John Chu · Fremont, US
• Sanjiv Mittal · Fremont, US
• John T. Orton · Los Altos, US
• Jagir S. Multani · Dix Hills, US
• Robert Jecmen · Pleasanton, US

Key dates

• Filing date: Jun 3, 1986
• Grant date: Oct 4, 1988
• Expiry date: Jun 3, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76819
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.