Latch circuit having two hold loops
US4779011A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1987 |
| Grant date | Oct 18, 1988 |
| Priority date | — |
| Expiry date | Mar 11, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit has two complementary hold loops therein for improving noise tolerance. The latch circuit includes a first gate for receiving a data and a first clock signal and outputting a first signal in response to a change in the clock signal. A second gate receives a second clock signal having an inverted polarity to that of the first clock signal. A third gate is operatively connected to output terminals of the first and second gates and outputs a first latch output. The latch circuit also includes a first hold line which supplies the first latch output to the second gate and a second hold line which supplies a second latch output of the latch circuit having an inverted polarity to that of the first latch output to the second gate. The second gate may have an inverted input terminal receiving the second latch output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.