Vector processor with a synchronously controlled operand fetch circuits
US4779192A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1984 |
| Grant date | Oct 18, 1988 |
| Priority date | — |
| Expiry date | Dec 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processor for sequentially reading out elements of a plurality of vector operands and sequentially storing the results of operations to the vector operands, comprising: operand counters for indicating the element numbers for every operand; address registers for every operand; a first comparator for comparing each element of the vector; maximum number registers for storing the maximum numbers of elements of the respective operands; a second comparator for comparing the operand counter of each operand with the content of the maximum number registers of each operand with respect to each operand; and a control circuit for independently updating the operand counters and operand address registers of ech operand in response to all of or parts of the outputs of the first and second comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.