Semiconductor memory device
US4779227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1986 |
| Grant date | Oct 18, 1988 |
| Priority date | — |
| Expiry date | Aug 12, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having data buses for connecting memory cells in memory cell arrays with input/output buffer circuit includes a plurality of memory cell arrays having repetitive patterns. In the device, a plurality of column decoders are adjacent to the memory cell arrays and have repetitive patterns. A portion of the column decoders is displaced from a regular location in the column decoder to a separate location on a substrate of the semiconductor memory device to leave a blank portion in the column decoder. The device also includes an input/output buffer circuit, data buses for connecting the memory cell arrays to the corresponding input/output buffer circuit through spaces outside the column decoders including the blank portion, and conductors for connecting the displaced portion of column decoders located in the separate location to the corresponding memory cell arrays through spaces outside the column decoders including the blank portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.