Process for fabricating electrically alterable floating gate memory devices
US4780424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1987 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Sep 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 .ANG. thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.