Control of cache buffer for memory subsystem
US4780808A · kind A · utility
54Cited by
14References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1987 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Oct 2, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid-state cache memory subsystem configured to be used in conjunction with disk drives for prestaging of data in advance of its being called for by a host computer features a controller featuring means for establishing and maintaining precise correspondence between storage locations in the solid-state array and on the disk memory, for use in establishing a reoriented position on a disk in the event of error detection, and in order to determine when a predetermined quantity of data has been read from the disk into the cache in a staging operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.