Vector processing apparatus providing vector and scalar processor synchronization
US4780811A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 2, 1986 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Jul 2, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processing apparatus includes a scalar processor for executing scalar instructions and a vector processor for executing vector instructions. The vector processing apparatus has status code registers (SCR) which can be referred to by both processors through a wait managing circuit. The scalar instructions each have an order assurance instruction to assure an order of execution, and the order assurance instruction and the vector instruction each have a field to designate an SCR. The wait managing circuit renders the execution of the instruction in the scalar processor or the vector processor to wait or enable in accordance with a set status or a reset status of the SCR designated by the instruction field, and sets or resets the SCR designated by the instruction field in response to the completion of execution of the instruction to control synchronization of the execution of instructions in both processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.