Semiconductor memory
US4780852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1986 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Jun 24, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, therby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.