Coplanar die to substrate bond method
US4781775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1987 |
| Grant date | Nov 1, 1988 |
| Priority date | — |
| Expiry date | Jun 1, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53178
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A coplanar die to substrate bond method wherein a plurality of die are aligned on a silicon wafer substrate in a predetermined relationship and a slurry of glass is applied to bond them together. This occurs while either on a flat or a grooved plate. When the silicon wafer substrate and the plurality of die are ready for firing, they are placed on a grooved plate so that grooves are below the glass thereby decreasing the capillary force which commonly causes overflow. With reduced overflow, the bonding can be done at a higher temperature to reduce underflow. Because there is no underflow or overflow using this process, a greater degree of coplanarity is achieved thereby making future processing steps, such as the processing of interconnect lines, much easier to perform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.