I.sup.2 t monitoring circuit
US4782422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1987 |
| Grant date | Nov 1, 1988 |
| Priority date | — |
| Expiry date | Jul 27, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/252
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An I.sup.2 t monitoring circuit utilizes a multiplier to provide a signal that is representative of the squared value of a monitored current. The squared signal minus a DC level is provided as an input to a voltage-to-frequency converter and the output of the voltage-to-frequency converter is provided as an input to a down counter. The down counter is configured to decrement a stored value in response to the frequency of pulses received from the voltage-to-frequency converter and provide a signal in response to the magnitude of the stored value being decremented to a first predetermined magnitude. Periodically, the magnitude of the stored value in the down counter is refreshed to a second predetermined magnitude. When a signal is received from the down counter to indicate that the magnitude of the stored value has been decremented to the first predetermined magnitude, the signal is latched and a continuing signal is provided to indicate that a trip should occur. The trip signal is provided so that external circuitry can respond by either disconnecting the load from the monitored current or taking steps to reduce the magnitude of the monitored current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.