Architecture for power of two coefficient FIR filter
US4782458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1986 |
| Grant date | Nov 1, 1988 |
| Priority date | — |
| Expiry date | Dec 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0232
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.