Programmable semiconductor read only memory device
US4782466A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1986 |
| Grant date | Nov 1, 1988 |
| Priority date | — |
| Expiry date | Sep 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable semiconductor read only memory device which includes a memory cell array formed by a plurality of memory cells arranged in a matrix arrangement. Each memory cell in the memory cell array includes a transistor having a gate thereof coupled to a word line, and a capacitor having an insulator layer, having a first terminal coupled to a bit line and having a second terminal coupled to the transistor so that the capacitor is grounded via the transistor. The insulator layer of the capacitor of a selected memory cell breaks down when a specific word line and a specific bit line coupled to the selected memory cell are driven, thereby making the capacitor conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.