Line power failure scheme for a gaming device
US4782468A · kind A · utility
51Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1986 |
| Grant date | Nov 1, 1988 |
| Priority date | — |
| Expiry date | Aug 5, 2006 |
Classification
- Technology area (CPC A)Human Necessities
- CPC primaryA63F2300/636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power failure scheme for a gaming device in which, upon the detection of a failure of the line power, particular processing operations are completed before power is completely lost. A regulated D.C. power supply coupled to the line power generates an interrupt having the highest priority upon detecting a failure of the line power. The main processor of the gaming device is responsive to a power fail interrupt to complete any access to a safe memory which may have been on-going at the time the interrupt was generated or to complete any state transition which was on-going at the time the interrupt was generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.