High speed/high drive CMOS output buffer with inductive bounce suppression
US4785201A · kind A · utility
36Cited by
6References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1986 |
| Grant date | Nov 15, 1988 |
| Priority date | — |
| Expiry date | Dec 29, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer is disclosed which employs a first pair of transistors connected in an (N-channel over P-channel) totem pole configuration, a second pair of transistors connected in a (P-channel over N-channel) totem pole configuration in parallel with the first pair of transistors, and a pair of inverters connected to delay the drive to the second pair of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.